Title :
Architecture and performance analysis of a DSP sub-system for multi-channel voice over network (VoN) gateways
Author :
Rayala, Jitendra ; Vemireddy, Krishna
Author_Institution :
VeriSilicon Inc., Santa Clara, CA, USA
Abstract :
A detailed system design methodology for architecting area optimized DSP sub-system for multi-channel voice gateways is presented. An architecture for a specific subsystem including memory organization and I/O bandwidth requirements is described. System level performance and characterization details of this sub-system in a 65 nm generic process are provided. It is shown that a substantial reduction of 75% in sub-system memory area is achieved with only a small increase of 17% in peak processing load.
Keywords :
Internet telephony; computer network performance evaluation; internetworking; signal processing; I/O bandwidth requirement; area optimized DSP subsystem; memory organization; multichannel voice gateways; multichannel voice over network gateways; performance analysis; system design methodology; Bandwidth; Digital signal processing; Logic gates; Memory management; Random access memory; System-on-a-chip; Time division multiplexing;
Conference_Titel :
Signal Processing and Communications (SPCOM), 2010 International Conference on
Conference_Location :
Bangalore
Print_ISBN :
978-1-4244-7137-9
DOI :
10.1109/SPCOM.2010.5560532
