Evaluation of various node configurations for fine-grain multithreading on stock processors

Author

Kim, Jin-Soo ; Ha, Soonhoi ; Jhon, Chu Shik

Author_Institution

Dept. of Comput. Eng., Seoul Nat. Univ., South Korea

fYear

1997

fDate

28 Apr-2 May 1997

Firstpage

349

Lastpage

354

Abstract

It becomes more and more interesting to construct multi-threaded parallel machines using stock processors due to their high performance/price ratio. However no quantitative analysis has been reported on the effectiveness of various node configurations and its impact on the overall performance. In this paper we explore three different node configurations in detail and compare their dynamic characteristics through instruction-level simulation with six benchmark programs. Our experiments show that employing a dedicated processor for communication and synchronization is a reasonable approach because it can almost double the performance. Several factors that limit the overall speedup are also presented

Keywords

cost-benefit analysis; multiprogramming; parallel architectures; parallel machines; performance evaluation; synchronisation; benchmark programs; dedicated processor; fine-grain multithreading; instruction-level simulation; multithreaded parallel machines; node configurations; performance; performance price ratio; quantitative analysis; speedup; stock processors; synchronization; Computational modeling; Concurrent computing; Contracts; Costs; Delay; Large-scale systems; Microprocessors; Multithreading; Parallel machines; Yarn;

fLanguage

English

Publisher

ieee

Conference_Titel

High Performance Computing on the Information Superhighway, 1997. HPC Asia '97

Conference_Location

Seoul

Print_ISBN

0-8186-7901-8

Type

conf

DOI

10.1109/HPC.1997.592172

Filename

592172