Advanced 300 mm Cu/CVD LK (k=2.2) multilevel damascene integration for 90/65 nm generation BEOL interconnect technologies

Author

Li, L.P. ; Lu, Y.C. ; Lu, H.H. ; Yang, Y.L. ; Lin, C.H. ; Chen, B.T. ; Liang, Ming ; Jang, S.M. ; Liang, M.S.

Author_Institution

Adv. Module Technol. Div., Taiwan Semicond. Manuf. Co., Hsin-Chu, Taiwan

fYear

2003

fDate

10-12 June 2003

Firstpage

105

Lastpage

106

Abstract

Nine-metal-level (9 ML) Cu/CVD low-k dielectric with k=2.2, Cu/LK (k=2.2), damascene integration on 300 mm wafers for 90/65 nm generation has been successfully demonstrated for the first time. To minimize line-line capacitance for least BEOL interconnect RC delay, no higher-k cap for Cu CMP or higher-k middle etch stop layers for metal trench etching were used in inter metal dielectric (IMD) film stacking. Integration challenges in the Cu/LK (k=2.2) damascene building were overcome by novel approaches in IMD film processing, Cu CMP and patterning. Excellent physical, electrical, reliability, and packaging results from this Cu/LK (k=2.2) BEOL interconnects are demonstrated.

Keywords

capacitance; copper; dielectric thin films; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; 300 mm; 65 nm; 90 nm; BEOL interconnection technology; CMP; Cu; RC delay; line-line capacitance; metal trench etching; multilevel damascene integration; nine metal level Cu/CVD low-k dielectric thin films; Capacitance; Damascene integration; Dielectric materials; Etching; Leakage current; Packaging; Stacking; Testing; Thermal resistance; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-033-X

Type

conf

DOI

10.1109/VLSIT.2003.1221108

Filename

1221108