Title :
Backside device physical analysis for yield and reliability of advanced bulk-Si CMOS ICs
Author :
Yuanjing Li ; Marks, Howard Lee
Author_Institution :
Silicon Failure Anal., nVidia Corp., Santa Clara, CA, USA
Abstract :
This paper presents an effective backside device physical analysis methodology for identification of defects and weaknesses from design or manufacturing in advanced flip-chip packaged bulk-Si CMOS ICs. Case studies demonstrate applications of the methodology and techniques in failure analysis and process evaluation of 28nm CMOS devices and beyond for yield and reliability enhancement.
Keywords :
CMOS integrated circuits; flip-chip devices; integrated circuit packaging; integrated circuit reliability; integrated circuit yield; advanced CMOS integrated circuit; backside device physical analysis; defect identification; flip-chip package; integrated circuit reliability; integrated circuit yield; size 28 nm; Dielectrics; Fuses; Logic gates; Scanning electron microscopy; Silicides; Silicon; Bulk silicon backside de-process; EBAC; FIB; OPC end-result; SEM; e-fuse;
Conference_Titel :
Reliability Physics Symposium, 2014 IEEE International
Conference_Location :
Waikoloa, HI
DOI :
10.1109/IRPS.2014.6860636
