Ge MOS characteristics with CVD HfO/sub 2/ gate dielectrics and TaN gate electrode

Author

Bai, W.P. ; Lu, N. ; Liu, J. ; Ramirez, Adrian ; Kwong, D.L. ; Wristers, D. ; Ritenour, A. ; Lee, L. ; Antoniadis, D.

Author_Institution

Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA

fYear

2003

fDate

10-12 June 2003

Firstpage

121

Lastpage

122

Abstract

In this paper, we report for the first time Ge MOS characteristics with ultra thin rapid thermal CVD HfO/sub 2/ gate dielectrics and TaN gate electrode. Using the newly developed pre-gate cleaning and NH/sub 3/-based Ge surface passivation, the TaN/HfO/sub 2//Ge gate stack with EOT of 12.9 /spl Aring/ exhibits excellent leakage current density of 6 mA/cm/sup 2/ @Vg=1V and interface state density (D/sub it/) of 8/spl times/10/sup 10//cm/sup 2/-eV. Both D/sub it/ and CV hysteresis of Ge MOS are improved significantly with NH/sub 3/ surface treatment. We also study the effects of post-deposition anneal and investigate the conduction mechanism of TaN/HfO/sub 2//Ge gate stack.

Keywords

CVD coatings; MOS capacitors; annealing; current density; dielectric hysteresis; germanium; hafnium compounds; hole mobility; interface states; leakage currents; passivation; surface treatment; tantalum compounds; thin films; Ge MOS properties; NH/sub 3/-based Ge surface passivation; TaN gate electrode; TaN-HfO/sub 2/-Ge; TaN/HfO/sub 2//Ge gate stack; conduction properties; dielectric hysteresis; interface state density; leakage current density; post-deposition annealing; surface treatment; ultra thin rapid thermal CVD HfO/sub 2/ gate dielectrics; Annealing; Cleaning; Dielectrics; Electrodes; Hafnium oxide; Hysteresis; Interface states; Leakage current; Passivation; Surface treatment;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-033-X

Type

conf

DOI

10.1109/VLSIT.2003.1221115

Filename

1221115