DocumentCode
1867582
Title
Micro analysis regarding package interconnection
Author
Hashimoto, Hideki
Author_Institution
Toray Res. Center, Inc., Tokyo, Japan
fYear
2015
fDate
June 29 2015-July 2 2015
Firstpage
122
Lastpage
125
Abstract
Useful characterization technique for packaging is illustrated with examples. It is found that 3D-SEM using a brand-new FIB system provides detailed structure and defects such as voids and cracks for flip-chip interconnections. Raman spectroscopy for TSV is useful for stress analysis. In order to observe barrier metal TEM is required because the barrier metal is very thin.
Keywords
flip-chip devices; integrated circuit interconnections; integrated circuit packaging; integrated circuit testing; scanning electron microscopy; stress analysis; three-dimensional integrated circuits; 3D-SEM; Raman spectroscopy; TSV; barrier metal TEM; brand new FIB system; crack defect; flip-chip interconnections; micro analysis; package interconnection; stress analysis; void defect; Flip-chip devices; Joints; Metals; Performance evaluation; Raman scattering; Stress; Three-dimensional displays;
fLanguage
English
Publisher
ieee
Conference_Titel
Physical and Failure Analysis of Integrated Circuits (IPFA), 2015 IEEE 22nd International Symposium on the
Conference_Location
Hsinchu
Type
conf
DOI
10.1109/IPFA.2015.7224348
Filename
7224348
Link To Document