DocumentCode
186775
Title
Improvement on CDM ESD robustness of high-voltage tolerant nLDMOS SCR devices by using differential doped gate
Author
Chen, Shih-Hung ; Linten, D. ; Scholz, Matthias ; Hellings, Geert ; Boschke, Roman ; Groeseneken, Guido ; Huang, Yi-Chun ; Ker, Ming-Dou
Author_Institution
imec, Leuven, Belgium
fYear
2014
fDate
1-5 June 2014
Abstract
Early failure has been observed during CDM ESD stress on high-voltage tolerant nLDMOS-SCR devices in a standard low-voltage CMOS technology due to the gate oxide (GOX) degradation. In this work, we propose a special p+/n+ differential doped gate which boosts the CDM ESD failure current level with a factor of 3 to 9.
Keywords
electrostatics; semiconductor device models; semiconductor device reliability; thyristors; CDM ESD failure current; CDM ESD robustness; charge device model; differential doped gate; gate oxide degradation; high voltage tolerant nLDMOS SCR device; standard low voltage CMOS technology; Degradation; Electric potential; Electrostatic discharges; Logic gates; Reliability; Stress; Thyristors; Electrostatic Discharge (ESD); gate oxide reliability; high-voltage tolerant (HVT) devices; laterally diffused nMOS (nLDMOS); transmission line pulsing (TLP) system; very fast TLP system (VFTLP);
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium, 2014 IEEE International
Conference_Location
Waikoloa, HI
Type
conf
DOI
10.1109/IRPS.2014.6860651
Filename
6860651
Link To Document