مرکز منطقه ای اطلاع رساني علوم و فناوري - An architecture for intermediate area-time complexity multiplier

DocumentCode :

1867863

Title :

An architecture for intermediate area-time complexity multiplier

Author :

Tamaru

fYear :

1993

fDate :

3-6 May 1993

Firstpage :

1825

Lastpage :

1828

Keywords :

Birth disorders; Computer architecture; Concurrent computing; Delay; Tree graphs; Wiring;

fLanguage :

English

Publisher :

ieee

Conference_Titel :

Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on

Conference_Location :

IEEE

Print_ISBN :

0-7803-1281-3

Type :

conf

Filename :

693026

Link To Document :