DocumentCode
1867961
Title
The P-SOG filling Shallow Trench Isolation technology for sub-70 nm device
Author
Jin-Hwa Heo ; Soo-Jin Hong ; Guk-Hyon Yon ; Yu-Gyun Shin ; Fujihara, K. ; U-In Chung ; Joo-Tae Moon
Author_Institution
Semicond. R&D Center, Samsung Electron. Co. Ltd., Kyungki, South Korea
fYear
2003
fDate
10-12 June 2003
Firstpage
155
Lastpage
156
Abstract
A novel Polysilazane-based inorganic Spin-On-Glass filling Shallow Trench Isolation (P-SOG filling STI) technology is developed for sub-70 nm devices, for the first time. A key processing step of this P-SOG filling STI technology is annealing after a CMP process. The post-CMP P-SOG annealing eliminates a field oxide recess problem. This technology shows good electrical characteristics compared with a HDP oxide filling STI. The P-SOG filling STI is a promising candidate for the future isolation technology.
Keywords
DRAM chips; annealing; chemical mechanical polishing; isolation technology; leakage currents; 70 nm; CMP annealing; STI; electrical properties; field oxide recess; polysilazane based inorganic spin-on-glass; shallow trench isolation technology; Annealing; Current measurement; Electric variables; Filling; Isolation technology; Leakage current; Moon; Random access memory; Research and development; Wet etching;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
4-89114-033-X
Type
conf
DOI
10.1109/VLSIT.2003.1221132
Filename
1221132
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