VLSI architecture design of motion vector processor for H.264/AVC

H.264/AVC has considerably complex derivation process of motion data in comparison with that of previous video standards. It mainly results from advanced motion vector prediction process to cope with various macroblock partitions and spatial/temporal direct modes. This paper addresses the efficient hardware design of the motion vector processor of full-compliant H.264/AVC High Profile (HP) decoder and its FPGA implementation. It has the processing capability of HD1080 (1920 times 1088) at 60 frames per second (fps) that is asymptotic to Level 4.2 of the standard. To do this, several design considerations are investigated and the solutions for them are presented. The proposed design was realized with 41 K logic gates and 4,608 bits SRAM at the operating frequency of 266 MHz and was completely conformed by means of Allegro compliance bitstreams on an FPGA platform.