The physical mechanism investigation of AC TDDB behavior in advanced gate stack

Author

Chen, C.L. ; Chang, S.W. ; Chen, S.C. ; Lee, Young-Hyun ; Lee, Yong Wook ; Huang, D.S. ; Shih, J.R. ; Wu, Kaijie

Author_Institution

Technol. Quality & Reliability Div., Taiwan Semicond. Manuf. Co., Ltd., Hsinchu, Taiwan

fYear

2014

fDate

1-5 June 2014

Abstract

For the first time, the physical mechanisms for both AC TDDB improvement and degradation are investigated. For an optimized gate stack, the AC TDDB improvement is due to more charge de-trapping. For a non-optimized gate stack, the AC TDDB degradation can be explained through a proposed model which combines the charge redistribution and charge recovery. In addition, the fast measurement could provide a more reliable TDDB lifetime projection due to the minimization of the charge trapping and de-trapping effects during the TDDB stress.

Keywords

MOSFET; high-k dielectric thin films; semiconductor device breakdown; semiconductor device reliability; AC TDDB behavior; HK-MG technology; TDDB stress; advanced gate stack; charge de-trapping effect; charge recovery; charge redistribution; charge trapping minimization; nMOSFETs; nonoptimized gate stack; optimized gate stack; physical mechanism; reliable TDDB lifetime projection; Degradation; Electron traps; Logic gates; Reliability; Stress; Velocity measurement; AC TDDB; bipolar; de-trap; lifetime; unipolar;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium, 2014 IEEE International

Conference_Location

Waikoloa, HI

Type

conf

DOI

10.1109/IRPS.2014.6860667

Filename

6860667