Improved fault localization method for power devices

Author

Huaping Lai ; Liao, Scott ; Wei Xu

Author_Institution

Quality & Reliability Assurance Div., Shanghai Huahong Grace Semicond. Manuf. Corp., Shanghai, China

fYear

2015

fDate

June 29 2015-July 2 2015

Firstpage

246

Lastpage

249

Abstract

Fault localization for power device is difficult due to their special structure with a thick metal layer on the surface as the testing terminal. This layer enhances the thermal diffusion and blocks the photon emission, which restricts the function of LC analysis, PEM or OBIRCH. The experiment shows that using the thinning layer like the barrier layer as the terminal after removing the most of the thick metal, the device remains the same status, while the PEM and OBIRCH work with high efficiency and defect could be located with much higher accuracy. The method is successfully applied for FA of conventional Power MOS, Super Junction, Diode and IGBT devices.

Keywords

fault location; insulated gate bipolar transistors; power MOSFET; power bipolar transistors; power semiconductor diodes; semiconductor device testing; thermal diffusion; IGBT devices; LC analysis; OBIRCH; PEM; barrier layer; diode devices; fault localization method; optical beam induced resistance change; photon emission; power MOS devices; power devices; super junction devices; thermal diffusion; thinning layer; Accuracy; Aluminum; Junctions; Photonics; Testing; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits (IPFA), 2015 IEEE 22nd International Symposium on the

Conference_Location

Hsinchu

Type

conf

DOI

10.1109/IPFA.2015.7224370

Filename

7224370