Title :
A design for digital, dynamic clock deskew
Author :
Dike, C.E. ; Kurd, N.A. ; Patra, P. ; Barkatullah, J.
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
Unintentional clock skews between clock domains represent an increasing and costly overhead in high-performance VLSI chips. We describe a novel yet easy-to-implement design that reduces skew between local clock domains dynamically or statically by sensing clock-delay differences and then tuning the clock of each domain relative to its neighbors. Lowering local clock skew is accomplished without compromising worst-case global skew.
Keywords :
VLSI; clocks; decision trees; delay circuits; VLSI chips; clock domains; digital clock deskew; dynamic clock deskew; local clock skew; sensing clock-delay; worst-case global skew; Clocks; Delay; Detectors; Frequency; Microprocessors; Phase detection; Temperature; Timing; Very large scale integration; Voltage;
Conference_Titel :
VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-034-8
DOI :
10.1109/VLSIC.2003.1221151
