Title :
Wafer level circuit analysis & micro-probing on open failure of voltage regulator device
Author :
Ang Chung Keow ; Bin Hashim, Ismail
Author_Institution :
Infineon Technol. (Kulim) Sdn Bhd, Kulim, Malaysia
fDate :
June 29 2015-July 2 2015
Abstract :
The increasing complexity of integrated circuits has made fault localization become difficult. This paper outlines the electrical fault localization process flow with circuit study and micro-probing measurement for further single device localization. Subsequently, physical defect of abnormal contact was identified at emitter terminal of P-type BJT thru mechanical cross section.
Keywords :
failure analysis; integrated circuit reliability; voltage regulators; wafer-scale integration; P-type BJT; electrical fault localization process flow; micro-probing; open failure; voltage regulator device; wafer level circuit analysis; Circuit faults; Current measurement; Failure analysis; Integrated circuits; Semiconductor device measurement; Transistors; Voltage measurement;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits (IPFA), 2015 IEEE 22nd International Symposium on the
Conference_Location :
Hsinchu
DOI :
10.1109/IPFA.2015.7224382
