Multi objective design space exploration of cache for embedded applications

High contribution of cache access power in the total power consumption of embedded processors has made it a major concern in embedded system designs. By technology scaling, leakage power has created more stress on design constraint and power budget of embedded processors. Therefore; designers require a comprehensive design space exploration of cache architecture. In this paper we find out the optimum performance per power consumption points for cache sizes based on design space exploration using a new energy model considering dynamic and leakage energy of cache for embedded applications. Full exploration is performed based on different feature sizes to find out the effect of technology scale down on power parameters of cache. Results show that in different feature sizes 30% of static power and 43 % of total power of an embedded core is consumed in the cache hierarchy in average. It means based on this work in smaller feature sizes and for embedded application that can tolerate performance lose up to 3%, we should select smaller cache hierarchy to deliver better performance per power as the most important parameter in designing embedded systems.