Title :
Open via with capacitive behaviour defect in scan logic failure analysis
Author_Institution :
Infineon Technol. (Kulim) Sdn Bhd, Kedah Darul Aman, Malaysia
fDate :
June 29 2015-July 2 2015
Abstract :
This paper describes analysis method on the nontrivial scan test failure eventually lead to the findings of defective via with capacitive interconnect. The observation of short time photon emission event and multiple spot locations that vary against fails vector are the challenging scenario of this fail mode.
Keywords :
design for testability; failure analysis; logic circuits; logic testing; capacitive behaviour defect; capacitive interconnect; nontrivial scan test failure; photon emission event; scan logic failure analysis; spot locations; Automatic test pattern generation; Failure analysis; Layout; Software; Transistors; Tungsten;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits (IPFA), 2015 IEEE 22nd International Symposium on the
Conference_Location :
Hsinchu
DOI :
10.1109/IPFA.2015.7224387
