DocumentCode
1868546
Title
Open via with capacitive behaviour defect in scan logic failure analysis
Author
Hashim, Ismail
Author_Institution
Infineon Technol. (Kulim) Sdn Bhd, Kedah Darul Aman, Malaysia
fYear
2015
fDate
June 29 2015-July 2 2015
Firstpage
314
Lastpage
317
Abstract
This paper describes analysis method on the nontrivial scan test failure eventually lead to the findings of defective via with capacitive interconnect. The observation of short time photon emission event and multiple spot locations that vary against fails vector are the challenging scenario of this fail mode.
Keywords
design for testability; failure analysis; logic circuits; logic testing; capacitive behaviour defect; capacitive interconnect; nontrivial scan test failure; photon emission event; scan logic failure analysis; spot locations; Automatic test pattern generation; Failure analysis; Layout; Software; Transistors; Tungsten;
fLanguage
English
Publisher
ieee
Conference_Titel
Physical and Failure Analysis of Integrated Circuits (IPFA), 2015 IEEE 22nd International Symposium on the
Conference_Location
Hsinchu
Type
conf
DOI
10.1109/IPFA.2015.7224387
Filename
7224387
Link To Document