Title :
0.622-8.0 Gbps 150 mW serial IO macrocell with fully flexible preemphasis and equalization
Author :
Farjad-Rad, R. ; Hiok-Taiq Ng ; Edward Lee, M.-J. ; Senthinathan, R. ; Dally, W.J. ; Nguyen, A. ; Rathi, R. ; Poulton, J. ; Edmondson, J. ; Tran, J. ; Yazdanmehr, H.
Author_Institution :
Velio Commun. Inc., Milpitas, CA, USA
Abstract :
This paper presents a 622 Mbps to 8 Gbps transceiver in standard 0.13 /spl mu/m CMOS technology. Each receiver and transmitter macrocell has its dedicated clock multiplication unit (CMU) and clock/data recovery unit (CDR), providing simultaneous multi-rate operation for multiple lanes on a chip. The transmitter and receiver front-end use direct 4:1 multiplex and 1:4 demultiplexing, using multiple-phase quarter-rate clocks. An automatic phase offset cancellation scheme is used to eliminate the phase mismatch of the multiple clock phases. Each transceiver occupies an active area of less than 0.4 mm/sup 2/ and consumes 150 mW at maximum speed.
Keywords :
CMOS integrated circuits; demultiplexing; integrated logic circuits; multiplexing; synchronisation; transceivers; 0.13 micron; 0.622 to 8 Gbit/s; 150 mW; CMOS technology; automatic phase offset cancellation; chip; clock multiplication unit; clock-data recovery unit; demultiplexing; multiple phase quarter rate clocks; multiplexing; receiver macrocell; transceiver macrocell; Backplanes; Bandwidth; CMOS technology; Clocks; Jitter; Macrocell networks; Switches; Transceivers; Transmitters; Very large scale integration;
Conference_Titel :
VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-034-8
DOI :
10.1109/VLSIC.2003.1221162
