A cost-efficient dynamic Ternary CAM in 130 nm CMOS technology with planar complementary capacitors and TSR architecture

Author

Noda, H. ; Inoue, Ken ; Mattausch, Hans Jurgen ; Koide, T. ; Arimoto, Keisuke

Author_Institution

ULSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan

fYear

2003

fDate

12-14 June 2003

Firstpage

83

Lastpage

84

Abstract

A novel dynamic Ternary-CAM (TCAM) architecture with transparently scheduled refresh, address-input-free writing and planar complementary capacitors is proposed. The planar dynamic concept allows small TCAM cell size of 4.79 /spl mu/m/sup 2/ in a 130 nm CMOS technology that is about half of the static TCAM cell size, and the complementary capacitors improve the stability of conventional-DRAM-based TCAM cells. Transparently scheduled refresh and address-input-free writing make the proposed TCAM especially attractive for classifying applications in network routers.

Keywords

CMOS memory circuits; DRAM chips; MOS capacitors; content-addressable storage; 130 nm; CMOS; DRAM; TSR architecture; content addressable memory; dynamic ternary CAM cell; planar complementary capacitors; static ternary CAM cell; CADCAM; CMOS technology; Capacitance; Capacitors; Clocks; Computer aided manufacturing; Random access memory; Read-write memory; Scheduling; Writing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-034-8

Type

conf

DOI

10.1109/VLSIC.2003.1221168

Filename

1221168