Destructive-read random access memory system buffered with destructive-read memory cache for SoC applications

Author

Ji, B.L. ; Munetoh, S. ; Chorng-Lii Hwang ; Wordeman, M. ; Kirihata, T.

Author_Institution

IBM Microelectron., Hopewell Junction, NY, USA

fYear

2003

fDate

12-14 June 2003

Firstpage

85

Lastpage

88

Abstract

This paper describes a novel random access memory system. The system is based on a destructive-read memory buffered by a destructive-read memory cache for hidden write back. SRAM comparable random access cycle time (tRC) is achieved, as tRC of the architecture is limited only by the destructive-read time of the memory array. By using a DRAM array as cache, the silicon area is reduced by about 25% from SRAM-cache system. Write back algorithms have been proved by mathematical models, and confirmed by simulations.

Keywords

DRAM chips; SRAM chips; cache storage; elemental semiconductors; semiconductor device models; silicon; DRAM array; SRAM cache system; Si; SoC applications; destructive read memory cache; destructive read random access memory; mathematical models; silicon; Buffer storage; Delay effects; Laboratories; Logic arrays; Logic circuits; Mathematical model; Microelectronics; Random access memory; Read-write memory; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-034-8

Type

conf

DOI

10.1109/VLSIC.2003.1221169

Filename

1221169