The Umbrella Cell: a logic-process-compatible 2T cell for SOC applications

Author

Akiyama, S. ; Oodaira, N. ; Ishikawa, T. ; Hisamoto, D. ; Watanabe, T.

Author_Institution

Central Res. Lab., Hitachi Ltd., Tokyo, Japan

fYear

2003

fDate

12-14 June 2003

Firstpage

89

Lastpage

92

Abstract

We propose the Umbrella Cell, a logic-process-compatible 2T-DRAM cell for SOC applications. The cell has two logic transistors and a planar MIM capacitor placed on a Cu wire above the transistors to form an umbrella-like structure. This requires one additional photo mask. Its area is 26 F/sup 2/, approximately 60% smaller than a 6T cell. Careful bias design and a sub-IV sensing scheme solve the coupling problems inherent to the cell and allow the use of thin-oxide logic transistors as well as operation at a bit-line voltage of 0.72 V.

Keywords

DRAM chips; MIM devices; alumina; capacitors; copper; integrated circuit design; tantalum; tantalum compounds; thin film transistors; 0.72 V; 2T-DRAM cell; Cu; Cu wire; SOC applications; Ta/sub 2/O/sub 5/-Al/sub 2/O/sub 3/-Ta; logic process compatible DRAM cell; photo mask; planar MIM capacitor; thin oxide logic transistors; umbrella cell; umbrella-like structure; Capacitance; Equivalent circuits; Fabrication; Laboratories; Logic; MIM capacitors; MOS capacitors; Random access memory; Voltage; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-034-8

Type

conf

DOI

10.1109/VLSIC.2003.1221170

Filename

1221170