2.4 Gb/s GaAs 8*8 time multiplexed switch integrated circuit

Author

Dick, G.W. ; Huisman, R.F. ; Jhee, Y.K. ; Nordin, R.A. ; Payne, W.A. ; Wyatt, K.W.

Author_Institution

AT&T Bell Lab., Reading, PA, USA

fYear

1989

fDate

22-25 Oct. 1989

Firstpage

101

Lastpage

104

Abstract

A 2.4-Gb/s GaAs 8*8 matrix switch for high-speed digital communication services has been designed, fabricated, and tested. The reconfiguration rate was designed to be at the data rate. A self-aligned refractory gate heterostructure FET technology (depletion mode) was chosen to implement the switch chip. The switch fabric was implemented in transmission gates to suppress crosstalk, minimize delay, minimize space, and lower power dissipation. The BFL (buffered FET logic) family was chosen for the logic gates. The 8*8 switch was designed to be nonblocking and provide multicast capability.<>

Keywords

III-V semiconductors; digital communication systems; digital integrated circuits; field effect integrated circuits; gallium arsenide; integrated logic circuits; multiplexing equipment; semiconductor switches; switching circuits; time division multiplexing; 2.4 Gbit/s; BFL; GaAs; TDM; buffered FET logic; crosspoint array; crosstalk suppression; data rate; depletion mode; digital IC; heterostructure FET technology; high-speed digital communication services; integrated circuit; matrix switch; multicast capability; nonblocking 8*8 switch; reconfiguration rate; self-aligned refractory gate; time multiplexed switch; transmission gates; Circuit testing; Communication switching; Digital communication; FETs; Fabrics; Gallium arsenide; Integrated circuit technology; Space technology; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1989. Technical Digest 1989., 11th Annual

Conference_Location

San Diego, CA, USA

Type

conf

DOI

10.1109/GAAS.1989.69303

Filename

69303