DocumentCode
1869225
Title
13.5-mW, 5-GHz WLAN, CMOS frequency synthesizer using a true single phase clock divider
Author
Pellerano, S. ; Samori, C. ; Levantino, S. ; Lacaita, A.L.
Author_Institution
Dipt. di Elettronica e Inf., Politecnico di Milano, Italy
fYear
2003
fDate
12-14 June 2003
Firstpage
145
Lastpage
148
Abstract
An integrated 5 GHz frequency synthesizer consuming only 5.4 mA from a 2.5 V supply is demonstrated in 0.25 /spl mu/m CMOS technology. The divider within the synthesizer employs the True Single Phase Clock logic. The output frequency spans from 5.14 to 5.70 GHz, with steps of 20 MHz. The reference spurs are -70 dBc and the phase noise is lower than -116 dBc/Hz at 1 MHz offset over the whole tuning range. The synthesizer is suitable for the HiperLAN II and the IEEE 802.11a standards.
Keywords
CMOS integrated circuits; frequency dividers; frequency synthesizers; phase locked loops; phase noise; 0.25 micron; 13.5 mW; 2.5 V; 20 MHz; 5 GHz; 5.14 to 5.70 GHz; 5.4 mA; CMOS frequency synthesizer; WLAN transceivers; phase noise; phase-locked loop; true single phase clock divider; true single phase clock logic; CMOS technology; Channel spacing; Clocks; Counting circuits; Flip-flops; Frequency synthesizers; Logic circuits; Phase locked loops; Phase noise; Wireless LAN;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
4-89114-034-8
Type
conf
DOI
10.1109/VLSIC.2003.1221185
Filename
1221185
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