Title :
A 5-GHz CMOS double-quadrature receiver for IEEE 802.11a applications
Author :
Wu, Chung-Yu ; Chou, Chung-Yun
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
A 5-GHz CMOS double-quadrature front-end receiver for Wireless-LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals and an active polyphase filter is designed to reject image signals. It has the advantages of low power dissipation, small chip area, and low sensitivity to parasitic components. Implemented in 0.18 um CMOS technology, the receiver chip can achieve 50.6 dB image-rejection with the power dissipation of 22.4 mW at 1.8-V voltage supply.
Keywords :
CMOS integrated circuits; active filters; phase shifters; radio receivers; wireless LAN; 0.18 micron; 1.8 V; 22.4 mW; 5 GHz; CMOS double quadrature receiver; CMOS technology; RF signals; active polyphase filter; parasitic components; phase shifter; power dissipation; receiver chip; sensitivity; wireless-LAN application; CMOS image sensors; CMOS technology; Filters; Power dissipation; RF signals; RLC circuits; Radio frequency; Signal generators; Signal to noise ratio; Voltage-controlled oscillators;
Conference_Titel :
VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-034-8
DOI :
10.1109/VLSIC.2003.1221186
