Title :
A Low Memory FPGA Based LDPC Decoder Architecture for Quasi-Cyclic LDPC codes
Author :
Saunders, P. ; Fagan, Anthony D.
Author_Institution :
Sch. of Electr., Electron. & Mech. Eng., Univ. Coll. Dublin
Abstract :
We propose a novel low memory fully programmable FPGA decoder architecture to decode quasi-cyclic LDPC codes. By performing optimizations at the code construction, algorithmic and architecture levels we are able to achieve significant memory storage advantages over current FPGA decoder implementations. Our decoder employs the modified turbo decoding algorithm, to achieve a memory utilisation of 71 Kb using a Xilinx Virtex-4 device
Keywords :
decoding; field programmable gate arrays; memory architecture; parity check codes; turbo codes; 71 Kbyte; FPGA decoder architecture; Xilinx Virtex-4 device; memory storage; optimization; quasicyclic LDPC codes; turbo decoding algorithm;
Conference_Titel :
Irish Signals and Systems Conference, 2006. IET
Conference_Location :
Dublin
Print_ISBN :
0-86341-665-9
