DocumentCode
1869621
Title
Study of substrate noise and techniques for minimization
Author
Mark Shane Peng ; Hae-Seung Lee
Author_Institution
Massachusetts Inst. of Technol., Cambridge, MA, USA
fYear
2003
fDate
12-14 June 2003
Firstpage
197
Lastpage
200
Abstract
This paper presents a study of substrate noise effects on analog circuits and a technique for minimizing substrate noise. Measured data of a 0.25 /spl mu/m CMOS test chip reveals that substrate noise couples through circuit asymmetries and nonlinearity, degrading analog circuit performance. An active substrate noise shaping circuit implemented on the same test chip demonstrates over 10 dB improvement in SNDR in the 0-20 kHz band of a delta-sigma modulator for substrate noise generated by an inverter array.
Keywords
CMOS analogue integrated circuits; capacitors; delta-sigma modulation; integrated circuit noise; 0 to 20 kHz; 0.2 micron; 10 dB; CMOS test chip; analog circuit; delta-sigma modulator; substrate noise shaping circuit; Analog circuits; CMOS analog integrated circuits; Circuit noise; Circuit testing; Coupling circuits; Degradation; Minimization; Noise measurement; Noise shaping; Semiconductor device measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
4-89114-034-8
Type
conf
DOI
10.1109/VLSIC.2003.1221201
Filename
1221201
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