Embedded twin MONOS flash memories with 4 ns and 15 ns fast access times

Author

Ogura, T. ; Ogura, N. ; Kirihara, M. ; Ki Tae Park ; Baba, Y. ; Sekine, M. ; Shimeno, K.

Author_Institution

Halo LSI Inc., New York, NY, USA

fYear

2003

fDate

12-14 June 2003

Firstpage

207

Lastpage

210

Abstract

By adding a shared bit diffusion contact to the twin MONOS, a high performance, low voltage, low power NOR-type memory can be achieved. The process is simple and the array maintains its dual density advantage, which makes this flash memory technology suitable for embedded as well as standalone applications. Two fast access embedded designs will be discussed: a) 16 Mb with 15 ns access time and b) 128 Kb with 4 ns access time.

Keywords

NOR circuits; flash memories; 128 KB; 15 ns; 16 MB; 4 ns; dual density; embedded twin MONOS flash memories; fast access embedded designs; low power NOR-type memory; shared bit diffusion contact; standalone applications; CMOS technology; Flash memory; Large scale integration; Logic arrays; Logic devices; Logic gates; Low voltage; MONOS devices; Nonvolatile memory; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-034-8

Type

conf

DOI

10.1109/VLSIC.2003.1221204

Filename

1221204

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1869708