Title :
A fully synchronized, pipelined, and re-configurable 50 Mb SRAM on 90 nm CMOS technology for logic applications
Author :
Zhang, K. ; Bhattacharya, U. ; Ma, L. ; Ng, Y. ; Zheng, B. ; Bohr, M. ; Thompson, S.
Author_Institution :
Portland Technol. Dev., Intel Corp., Hillsboro, OR, USA
Abstract :
A 50 Mb SRAM chip is designed and fabricated on an industry leading 90 nm CMOS technology that features a 1 /spl mu/m/sup 2/ SRAM cell and 50 nm gate length transistors with strained silicon. The SRAM chip is formed with 100/spl times/512 Kb subarrays that have 2.5 GHz nominal operating frequency, 75% area efficiency, and fully synchronized internal timing along with efficient local power-down feature. And the design can be easily re-configured to form large high-density on-die cache memory for high-speed logic applications such as CPUs.
Keywords :
CMOS integrated circuits; SRAM chips; cache storage; elemental semiconductors; logic gates; silicon; 2.5 GHz; 50 nm; 90 micron; CMOS technology; CPU; SRAM; SRAM chip; Si; die cache memory; high speed logic applications; silicon; transistors; CMOS logic circuits; CMOS technology; Cache memory; Frequency synchronization; Logic design; Random access memory; SRAM chips; Silicon; Textile industry; Timing;
Conference_Titel :
VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-034-8
DOI :
10.1109/VLSIC.2003.1221219
