Title :
The endurance of EEPROMs/utilizing fault tolerant memory cells
Author :
Haifley, T. ; Sowards, D.
Author_Institution :
EXAR Corp., San Joase, CA, USA
Abstract :
A triple modular redundant (TMR) electrically erasable programmable read only memory (EEPROM) cell design used for on-chip error correction is described. It can be used in applications where high reliability and high endurance are required. A mathematical reliability model used to assess the effectiveness of this fault-tolerant structure is also presented. Since the TMR EEPROM cell is available in a standard-cell semicustom integrated circuit (IC) family, the model can be used to assess fault tolerance for any semicustom ICs which use the fault-tolerant EEPROM circuitry. The fault-tolerant scheme is shown to provide endurance and reliability beyond that for EEPROM cells which do not have on-chip error correction
Keywords :
EPROM; application specific integrated circuits; fault tolerant computing; integrated memory circuits; ASIC; EEPROM; design; endurance; failures; fault tolerant memory cells; mathematical reliability model; on-chip error correction; semicustom integrated circuit; triple modular redundant; Application specific integrated circuits; Charge carrier processes; EPROM; Electrons; Error correction codes; Fault tolerance; Manufacturing; Nonvolatile memory; Semiconductor device doping; Voltage;
Conference_Titel :
Reliability and Maintainability Symposium, 1990. Proceedings., Annual
Conference_Location :
Los Angeles, CA
DOI :
10.1109/ARMS.1990.67987
