Title :
A CMOS 33-mW 100-MHz 80-dB SFDR sample-and-hold amplifier
Author :
Cheng-Chung Hsu ; Jieh-Tsorng Wu
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
A high-speed high-resolution sample-and-hold amplifier (SHA) is designed for time-interleaved analog-to-digital converter applications. Using the techniques of precharging and output capacitor coupling can mitigate the stringent performance requirements for the opamp, resulting in low power dissipation. Implemented in a standard 0.25 /spl mu/m CMOS technology, the SHA achieves 80 dB spurious-free dynamic range (SFDR) for a 1.8 Vpp output at 100 MHz Nyquist sampling rate. The SHA occupies a die area of 0.35 mm/sup 2/ and dissipates 33 mW from a single 2.5 V supply.
Keywords :
CMOS integrated circuits; Nyquist diagrams; amplifiers; analogue-digital conversion; capacitance; integrated circuit design; sample and hold circuits; 0.25 micron; 100 MHz; 2.5 V; 33 mW; 80 dB; CMOS; Nyquist sampling; SFDR sample; analog-digital converter; high-speed high-resolution sample; hold amplifier; low power dissipation; mitigate performance; operational amplifier; output capacitor coupling; precharging; spurious-free dynamic range; stringent performance; Bandwidth; CMOS technology; Capacitors; Clocks; Design engineering; Dynamic range; Power dissipation; Power engineering and energy; Sampling methods; Switches;
Conference_Titel :
VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-034-8
DOI :
10.1109/VLSIC.2003.1221222
