Stability Analysis Of High Frequency Digital Phase Locked Loops using Piecewise Linear Model

This paper considers the stability of high frequency digital phase lock loops (DPLL). Traditional design techniques are excessively conservative for high frequency, high order DPLL systems. This paper proposes an accurate and efficient means of identifying stable regions for 2^nd and 3^rd order high frequency DPLL. Using an accurate non-linear DPLL simulation it is shown that the proposed stability technique is a significant improvement over existing linear methods