Title :
Efficient on-chip global interconnects
Author :
Ho, R. ; Mai, K. ; Horowitz, M.
Author_Institution :
Comput. Syst. Lab., Stanford Univ., CA, USA
Abstract :
We present circuits for a high-efficiency low-swing interconnect scheme suitable for the Smart Memories reconfigurable architecture. By using a separate supply, global clocking, and differential signaling, we reduce design complexity; and by using overdrive circuits, equalization techniques, and sense-amplifiers we retain high performance. A testchip built in a 1.8 V 0.18-/spl mu/m technology consumed <1pJ/bit for a 10 mm bus at 1 GHz, a power savings over full-swing signaling of up to 10 x, and demonstrated amplifier input offset voltages of under 100 mV.
Keywords :
integrated circuit design; integrated circuit interconnections; integrated memory circuits; 0.18 micron; 1.8 V; 10 mm; 100 mV; chip global interconnects; differential signaling; equalization techniques; global clocking; high-efficiency low-swing interconnect; input offset voltages; sense-amplifiers; smart memories chip; smart memories reconfigurable architecture; Circuit testing; Clocks; Computer architecture; Degradation; Delay; Integrated circuit interconnections; Memory architecture; Network-on-a-chip; Repeaters; Wires;
Conference_Titel :
VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-034-8
DOI :
10.1109/VLSIC.2003.1221224
