DocumentCode
1870253
Title
A low cost high performance register-controlled digital DLL for 1 Gbps/spl times/32 DDR SDRAM
Author
Jong-Tae Kwak ; Chang-Ki Kwon ; Kwan-Weon Kim ; Seong-Hoon Lee ; Joong-Sik Kih
Author_Institution
Memory R&D Div., Hynix Semicond. Inc., Kyoungki, South Korea
fYear
2003
fDate
12-14 June 2003
Firstpage
283
Lastpage
284
Abstract
A low cost high performance register-controlled digital delay-locked loop (DLL) that has novel resolution-enhancing structure with inherent duty cycle correction capability was developed for 1 Gbps/spl times/32 DDR SDRAM. Experimental results in a 0.13 /spl mu/m 4 M/spl times/32 DDR SDRAM show <25 ps peak-to-peak jitter with quiet supply, \n\n\t\t
Keywords
DRAM chips; delay lock loops; digital phase locked loops; jitter; 0.13 micron; 1.8 V; 2.5 V; 24 mW; 60 mW; 66 to 500 MHz; SDRAM; digital delay-locked loop; duty cycle correction; peak-peak jitter; register-controlled digital DLL; Costs; DRAM chips; Delay effects; Delay lines; Error correction; Impedance; Inverters; Jitter; Research and development; Time to market;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
4-89114-034-8
Type
conf
DOI
10.1109/VLSIC.2003.1221227
Filename
1221227
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