Improve latch-up immunity by circuit solution

Author

Hui-Wen Tsai ; Ming-Dou Ker

Author_Institution

Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu, Taiwan

fYear

2015

fDate

June 29 2015-July 2 2015

Firstpage

527

Lastpage

530

Abstract

A concept of active guard ring and its corresponding circuit solution to enhance the latch-up immunity of integrated circuits (IC) are proposed and verified in a 0.6-um 5-V CMOS process. By detecting the over-shooting/under-shooting trigger current during latchup current test (I-test), some compensation current generated from on-chip ESD PMOS or NMOS devices through special circuit design can effectively reduce the latchup trigger current that injecting into the core circuit blocks. Therefore, the latchup immunity of I-test with positive or negative trigger current applied at the I/O pins can be significantly improved.

Keywords

CMOS logic circuits; flip-flops; logic design; logic testing; trigger circuits; CMOS process; I-O pins; I-test; IC; NMOS devices; active guard ring; circuit design; circuit solution; compensation current; integrated circuits; latch-up immunity; latchup current test; latchup trigger current; on-chip ESD PMOS devices; over-shooting trigger current; size 0.6 mum; under-shooting trigger current; voltage 5 V; Art; CMOS integrated circuits; Electrostatic discharges; Layout; Logic gates; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits (IPFA), 2015 IEEE 22nd International Symposium on the

Conference_Location

Hsinchu

Type

conf

DOI

10.1109/IPFA.2015.7224450

Filename

7224450