Title :
Three-pattern tests for delay faults
Author :
Franco, Piero ; McCluskey, Edward J.
Author_Institution :
Center for Reliable Comput., Stanford Univ., CA, USA
Abstract :
To improve the quality of CMOS digital circuits, more complex fault models than single stuck-at have been proposed. This paper focuses on the effect of inaccurate delay modeling on delay fault testing. It is shown that accurate delay models are needed for effective delay fault testing. This is particularly important for large timing optimized circuits with many paths. Limitations of the path delay fault model are shown, and even the assumption that 2-pattern tests are sufficient for delay testing is shown to have limitations
Keywords :
CMOS integrated circuits; automatic testing; fault location; integrated circuit testing; integrated logic circuits; logic testing; CMOS digital circuits; delay fault testing; fault models; inaccurate delay modeling; path delay; three-pattern tests; timing optimized circuits; CMOS digital integrated circuits; Circuit faults; Circuit testing; Delay effects; Digital circuits; Logic testing; Parasitic capacitance; Propagation delay; Robustness; Semiconductor device modeling;
Conference_Titel :
VLSI Test Symposium, 1994. Proceedings., 12th IEEE
Conference_Location :
Cherry Hill, NJ
Print_ISBN :
0-8186-5440-6
DOI :
10.1109/VTEST.1994.292274
