Title :
On evaluating competing bridge fault models for CMOS ICs
Author :
Chess, Brian ; Roth, Carl ; Larrabee, Tracy
Author_Institution :
Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
Abstract :
Compares the accuracy, speed and applicability to test generation of existing bridge fault modeling solutions. The authors identify some previously undiscussed anomalous circuit behaviors, and describe the extent to which they affect bridge fault simulation and testing. Finally, they present a system for evaluating bridge fault models in a test generation environment, and present an experiment that provides an assessment of how defect coverage can be affected by a generating and checking model
Keywords :
CMOS integrated circuits; automatic testing; fault location; integrated circuit testing; integrated logic circuits; logic testing; CMOS ICs; anomalous circuit behaviors; checking model; competing bridge fault models; defect coverage; defect testing; generating model; logic circuits; test generation; Bridge circuits; CMOS logic circuits; Circuit faults; Circuit testing; Integrated circuit modeling; Integrated circuit testing; Predictive models; Semiconductor device modeling; System testing; Voltage;
Conference_Titel :
VLSI Test Symposium, 1994. Proceedings., 12th IEEE
Conference_Location :
Cherry Hill, NJ
Print_ISBN :
0-8186-5440-6
DOI :
10.1109/VTEST.1994.292275
