Title :
Gate-to-channel shorts in BiCMOS logic gates
Author :
Chen, C.-J. ; Mourad, S.
Author_Institution :
Dept. of Electr. Eng., Santa Clara Univ., CA, USA
Abstract :
This paper describes the effects of gate-to-channel breakdown on the operation of BiCMOS logic gates. Both the static and dynamic behaviours of the gates are examined. The influence of the position of the defect within the channel is noted. Expressions for the logic levels and the quiescent current of an inverter in the presence of defects are calculated as an example. SPICE simulations confirmed the results and were used with other logic gates. The experimental results show that gate-to-channel breakdown cannot be modeled by a stuck-at fault. Iddq testing is more effective than delay testing in detecting these effects. Test patterns for Iddq are given
Keywords :
BiCMOS integrated circuits; SPICE; digital simulation; logic gates; logic testing; BiCMOS logic gates; Iddq testing; SPICE simulations; dynamic behaviour; gate-to-channel breakdown; gate-to-channel shorts; logic levels; quiescent current; static behaviour; test patterns; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Circuit faults; Circuit testing; Electric breakdown; Inverters; Logic gates; Logic testing; SPICE;
Conference_Titel :
VLSI Test Symposium, 1994. Proceedings., 12th IEEE
Conference_Location :
Cherry Hill, NJ
Print_ISBN :
0-8186-5440-6
DOI :
10.1109/VTEST.1994.292276
