Title :
Eliminating undetectable shorts between horizontal wires during channel routing
Author :
McGowen, Richard ; Ferguson, F.J.
Author_Institution :
Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
Abstract :
Presents a procedure for reducing the probability of undetectable shorts occurring between horizontal wires. This procedure is implemented by modifying a channel router to predict many of the shorts that are undetectable and then place the associated signal wires in nonadjacent tracks. For the designs routed, it is found that the probability of an undetectable nonfeedback short between horizontal lines in the routing channels is reduced by 39.9% with no increase in the number of routing tracks required and little increase in routing computation cost
Keywords :
CMOS integrated circuits; integrated circuit testing; integrated logic circuits; logic CAD; logic testing; network routing; probability; ATPG; CMOS logic circuits; channel routing; horizontal wires; nonadjacent tracks; probability; routing computation cost; signal wires; undetectable nonfeedback short; undetectable shorts; CMOS technology; Circuit faults; Computational efficiency; Delay; Integrated circuit interconnections; Routing; Steady-state; Testing; Timing; Wires;
Conference_Titel :
VLSI Test Symposium, 1994. Proceedings., 12th IEEE
Conference_Location :
Cherry Hill, NJ
Print_ISBN :
0-8186-5440-6
DOI :
10.1109/VTEST.1994.292282
