Title :
Analysis of IDDQ detectable bridges in combinational CMOS circuits
Author :
Isern, E. ; Figueras, J.
Author_Institution :
Dept. d´´Enginyeria Electronica, Univ. Politecnica de Catalunya, Barcelona, Spain
Abstract :
Functionally equivalent nodes may cause some bridging faults to become undetectable by IDDQ testing. An efficient method for the identification of classes of functionally equivalent nodes in combinational circuits, based on OBDD comparison, is presented. To illustrate the methodology, the IDDQ undetectable logic bridging faults have been identified in a set of benchmark circuits
Keywords :
CMOS integrated circuits; combinatorial circuits; integrated logic circuits; logic testing; redundancy; IDDQ detectable bridges; OBDD comparison; benchmark circuits; combinational CMOS circuits; functionally equivalent nodes; undetectable logic bridging faults; Bridge circuits; CMOS logic circuits; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Inverters; Logic circuits; Logic testing; Redundancy;
Conference_Titel :
VLSI Test Symposium, 1994. Proceedings., 12th IEEE
Conference_Location :
Cherry Hill, NJ
Print_ISBN :
0-8186-5440-6
DOI :
10.1109/VTEST.1994.292287
