Title :
On broad-side delay test
Author :
Savir, Jacob ; Patil, Srinivas
Author_Institution :
Microelectronics Div., IBM Corp., Austin, TX, USA
Abstract :
A broad-side delay test is a form of a scan-based delay test, where the first vector of the pair is scanned into the chain, and the second vector of the pair is the combinational circuit´s response to this first vector. This delay test form is called “broad-side” since the second vector of the delay test pair is provided in a broad-side fashion, namely through the logic. This paper concentrates on generation of broad-side delay test vectors; shows the results of experiments conducted on the ISCAS sequential benchmarks, and discusses some concerns of the broad-side delay test strategy
Keywords :
boundary scan testing; combinatorial circuits; logic testing; sequential circuits; ISCAS sequential benchmarks; broad-side delay test; combinational circuit; delay test pair; scan-based delay test; test strategy; test vectors; Circuit faults; Circuit testing; Clocks; Delay effects; Jacobian matrices; Logic circuits; Logic testing; Microelectronics; Propagation delay; Sequential analysis;
Conference_Titel :
VLSI Test Symposium, 1994. Proceedings., 12th IEEE
Conference_Location :
Cherry Hill, NJ
Print_ISBN :
0-8186-5440-6
DOI :
10.1109/VTEST.1994.292299
