DocumentCode :
1871465
Title :
FACTS: fault coverage estimation by test vector sampling
Author :
Heragu, Keerthinarayan ; Agrawal, Vishwani D. ; Bushnell, Michael L.
Author_Institution :
Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
fYear :
1994
fDate :
25-28 Apr 1994
Firstpage :
266
Lastpage :
271
Abstract :
We propose a new statistical technique for estimating fault coverage in combinational circuits. Our method requires fault-free simulation of a random sample of vectors from the test vector set. Fault coverage is computed from controlabilities and observabilities both defined as probabilities and the method is applicable to any fault model like stuck-at-faults or delay faults. Experimental results are presented for path and transition delay faults
Keywords :
combinatorial circuits; controllability; delays; fault location; logic testing; observability; probability; statistical analysis; FACTS; combinational circuits; controlabilities; delay faults; fault coverage estimation; fault model; fault-free simulation; observabilities; probabilities; statistical technique; stuck-at-faults; test vector sampling; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Delay; Electrical fault detection; Fault detection; Observability; Probability; Sampling methods;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 1994. Proceedings., 12th IEEE
Conference_Location :
Cherry Hill, NJ
Print_ISBN :
0-8186-5440-6
Type :
conf
DOI :
10.1109/VTEST.1994.292302
Filename :
292302
Link To Document :
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