Author :
Zhang, Dejing ; Kang, L. ; Goedeke, D. ; Nagy, A. ; Dhandapani, V. ; Hildreth, J. ; Fu, C.C. ; Kropewnicki, T. ; Jahanbani, M. ; Martinez, H. ; Noble, R. ; Eades, D. ; Nguyen, B.Y. ; Kolagunta, V. ; Hall, M. ; Cheek, J. ; Venkatesan, S.
Abstract :
This paper presents a detailed study of SOI source/drain embedded SiGe (eSiGe) technology with a focus on parasitic characteristics. It shows that eSiGe can appreciably suppress on-state floating body effect and improve device exterior resistance. Although eSiGe only physically addresses P-FET, junction capacitances of both P- and N-FETs can be impacted.
Keywords :
Ge-Si alloys; field effect integrated circuits; field effect transistors; silicon-on-insulator; N-FET; P-FET; SOI eSiGe technology; SOI source/drain embedded SiGe technology; SiGe; device exterior resistance; junction capacitance; on-state floating body effect; parasitic characteristics; Capacitive sensors; Conference proceedings; Doping; Epitaxial growth; Etching; Germanium silicon alloys; Immune system; Silicon germanium; Thermal stresses; USA Councils;
