Title :
Sequential test generation with reduced test clocks for partial scan designs
Author :
Lee, Soo Y. ; Saluja, Kewal K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
Abstract :
Partial scan design technique is often preferred to full scan because the use of smaller number of scan flip-flops leads to less performance degradation and less overhead. However, the number of clocks required to apply a test vector is proportional to the number of flip-flops in the scan path whenever scan is performed. This tends to increase the test application considerably. In this paper we presents an algorithm to generate a test with fewer test clocks for partial scan designs by using sequential test generation and scan strategies. The objective is to find a test that requires less test clocks while achieving high fault coverage. The algorithm, Test Application time Reduction for Partial scan design (TARP), is implemented and tested on a set of ISCAS sequential benchmark circuits. The algorithm produces a test with substantial reduction in the number of test clocks, compared to a test in which each test vector is associated with a scan operation
Keywords :
automatic testing; design for testability; integrated circuit testing; integrated logic circuits; logic design; logic testing; sequential circuits; TARP algorithm; high fault coverage; partial scan designs; scan flip-flops; sequential test generation; test clocks; test vector; Algorithm design and analysis; Circuit faults; Circuit testing; Clocks; Costs; Degradation; Flip-flops; Hardware; Production; Sequential analysis;
Conference_Titel :
VLSI Test Symposium, 1994. Proceedings., 12th IEEE
Conference_Location :
Cherry Hill, NJ
Print_ISBN :
0-8186-5440-6
DOI :
10.1109/VTEST.1994.292309