DocumentCode
1871719
Title
On compacting test sets by addition and removal of test vectors
Author
Kajihara, Seiji ; Pomeranz, Irith ; Kinoshita, Kozo ; Reddy, Sudhakar M.
Author_Institution
Dept. of Appl. Phys., Osaka Univ., Japan
fYear
1994
fDate
25-28 Apr 1994
Firstpage
202
Lastpage
207
Abstract
This paper presents a method of test compaction for stuck-at faults in combinational circuits, that complements previously proposed methods and allows further reduction in test set size in a cost-effective way. A given test set is compacted by generating additional test vectors. Each test vector added allows the removal of two or more test vectors from the existing test set, thus reducing its size. Experimental results for benchmark circuits demonstrate the effectiveness of the method
Keywords
combinatorial circuits; integrated circuit testing; integrated logic circuits; logic testing; combinational circuits; stuck-at faults; test compaction; test set size reduction; test vector addition; test vector removal; Circuit faults; Circuit testing; Cities and towns; Combinational circuits; Compaction; Computational modeling; Fault detection; Flip-flops; Physics computing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1994. Proceedings., 12th IEEE
Conference_Location
Cherry Hill, NJ
Print_ISBN
0-8186-5440-6
Type
conf
DOI
10.1109/VTEST.1994.292312
Filename
292312
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