Title :
Limitations in predicting defect level based on stuck-at fault coverage
Author :
Park, Jaehong ; Naivar, Mark ; Kapur, Rohit ; Mercer, M. Ray ; Williams, T.W.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Abstract :
The stuck-at fault model has been used over decades as a guide to the test generation process and as an evaluation mechanism for the quality of the test set. As demands on quality have increased, the use of the stuck-at fault model as a predictor of the defect level has been questioned. This paper provides some insight on the issue and shows the limitations of using the stuck-at fault coverage to predict the defect level. The authors demonstrate that as defect level decreases the uncertainty of the estimate grows
Keywords :
CMOS integrated circuits; automatic testing; fault location; integrated circuit testing; integrated logic circuits; logic testing; defect level; estimate uncertainty; logic circuits; stuck-at fault coverage; test generation process; test set quality; Circuit faults; Circuit testing; Contracts; Design for testability; Integrated circuit modeling; Manufacturing processes; Performance analysis; Performance evaluation; Predictive models; System testing;
Conference_Titel :
VLSI Test Symposium, 1994. Proceedings., 12th IEEE
Conference_Location :
Cherry Hill, NJ
Print_ISBN :
0-8186-5440-6
DOI :
10.1109/VTEST.1994.292315
