DocumentCode
1871914
Title
Code disjoint self-parity combinational circuits for self-testing, concurrent fault detection and parity scan design
Author
Goessel, M. ; Sogomonyan, E.S.
Author_Institution
Fault-Tolerant Computing Group, Potsdam Univ., Germany
fYear
1994
fDate
25-28 Apr 1994
Firstpage
151
Lastpage
157
Abstract
In this paper it is shown how an arbitrary n-tupel of m-ary Boolean functions can be systematically implemented as a code-disjoint self-testing combinational circuit. This is achieved by the use of a parity bit of the inputs and a parity bit of the outputs, a second additional output and of one or more replicates of a selected part of the monitored circuit. The parity bit of the outputs and the functional bits are thus jointly designed rather than in separation. The circuit can be used in test mode, in scan-test mode if it is the combinational part of a sequential circuit, and in normal operation mode for concurrent fault detection. In normal on-line operation, faults may be detected with some degree of latency
Keywords
Boolean functions; boundary scan testing; combinatorial circuits; fault location; logic testing; arbitrary n-tupel; code-disjoint self-testing combinational circuit; concurrent fault detection; latency; m-ary Boolean functions; monitored circuit; parity bit; parity scan design; scan-test mode; self-parity combinational circuits; Boolean functions; Built-in self-test; Circuit faults; Circuit testing; Combinational circuits; Electrical fault detection; Fault detection; Monitoring; Sequential analysis; Sequential circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1994. Proceedings., 12th IEEE
Conference_Location
Cherry Hill, NJ
Print_ISBN
0-8186-5440-6
Type
conf
DOI
10.1109/VTEST.1994.292320
Filename
292320
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