Title :
Novel architectures for TSC/CD and SFS/SCD synchronous controllers
Author :
Kia, S.M. ; Parameswaran, S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Queensland Univ., St. Lucia, Qld., Australia
Abstract :
Introduces design models for totally self checking, code disjoint (TSC/CD) and strongly fault secure, strongly code disjoint (SFS/SCD) synchronous controllers. The TSC/CD and SFS/SCD models are based on two new proposed low-cost, modular, totally self checking (TSC), edge triggered and error propagating (code disjoint) flip-flops; one, a D flip-flop which can be used in TSC and strongly fault secure (SFS) synchronous circuits with two-rail codes; the other a T flip-flop, used in a similar way as the D flip-flop but retaining the error as an indicator until the next presetting, as an aid to error propagation
Keywords :
circuit reliability; flip-flops; logic testing; sequential circuits; D flip-flop; SFS/SCD models; T flip-flop; TSC/CD models; edge triggered flip-flops; error propagating flip-flops; error propagation; presetting; strongly fault secure strongly code disjoint; synchronous controllers; totally self checking code disjoint; two-rail codes; Automatic testing; Built-in self-test; Circuit faults; Clocks; Complexity theory; Computer architecture; Flip-flops; Rails; Very large scale integration;
Conference_Titel :
VLSI Test Symposium, 1994. Proceedings., 12th IEEE
Conference_Location :
Cherry Hill, NJ
Print_ISBN :
0-8186-5440-6
DOI :
10.1109/VTEST.1994.292322
