• DocumentCode
    1871943
  • Title

    Evaluation and Optimization of FinFET Quantization Error in Porting a Design from Planar Silicon Technology

  • Author

    Rao, R. ; Kim, J. ; Chuang, C.T.

  • Author_Institution
    IBM T. J. Watson Res. Center, Yorktown Heights, NY
  • fYear
    2007
  • fDate
    1-4 Oct. 2007
  • Firstpage
    49
  • Lastpage
    50
  • Abstract
    A methodology for evaluation and optimization of quantization error when porting a pre-existing planar design to FinFET technology is presented. A 52-bit adder from a general purpose processor is used to illustrate the key findings of this study.
  • Keywords
    MOSFET; adders; error analysis; silicon-on-insulator; 52-bit adder; FinFET quantization error; SiO2-Si; general purpose processor; planar silicon technology; pre-existing planar design; CMOS technology; Conference proceedings; Constraint optimization; Design optimization; FinFETs; Fingers; Physics computing; Process design; Quantization; Silicon;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference, 2007 IEEE International
  • Conference_Location
    Indian Wells, CA
  • ISSN
    1078-621X
  • Print_ISBN
    978-1-4244-0879-5
  • Electronic_ISBN
    1078-621X
  • Type

    conf

  • DOI
    10.1109/SOI.2007.4357846
  • Filename
    4357846
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1871943