Title :
Test generation and three-state elements, buses, and bidirectionals
Author :
Van der Linden, J. Th ; Konijnenburg, M.H. ; van de Goor, A.J.
Author_Institution :
Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
Abstract :
Published work on stuck-at-fault test generation nearly exclusively considers circuits composed of only binary logic gates. Industrial designs commonly contain three-state elements, such as: buses and drivers, transmission gates, and bidirectional I/O. This paper presents extensions to state-of-the-art ATPG algorithms in order to handle these elements. A 25-valued signal model is used for test generation. Results demonstrate the effectiveness of the proposed extensions in the presence of various three-state elements, and show but a small performance degradation compared to the traditional 9-valued signal model for binary logic circuits
Keywords :
automatic testing; logic testing; ternary logic; 25-valued signal model; ATPG algorithms; automatic test pattern generation; bidirectional I/O; three-state buses; three-state elements; Automatic test pattern generation; Circuit simulation; Circuit testing; Flip-flops; Logic circuits; Logic testing; Signal generators; Switches; System testing; Wires;
Conference_Titel :
VLSI Test Symposium, 1994. Proceedings., 12th IEEE
Conference_Location :
Cherry Hill, NJ
Print_ISBN :
0-8186-5440-6
DOI :
10.1109/VTEST.1994.292325
