ICAT: incremental combinational ATPG

Author

So, Byung S. ; Kime, Charles R.

Author_Institution

Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA

fYear

1994

fDate

25-28 Apr 1994

Firstpage

106

Lastpage

113

Abstract

An incremental ATPG system for combinational circuits, ICAT, is presented. ICAT uses the hypothesis that, if a circuit modification is small, the old tests for the circuit before modification can provide crucial information to speed up generation of new tests for the modified circuit. Four incremental techniques in ICAT maximally utilize information from the old tests with minimal storage requirements. The four incremental techniques are augmented with a fast, effective deterministic test generation algorithm in ICAT. The experimental results from the evaluation of three different classes of modifications to ISCAS circuits show the incremental technique to be efficient and effective

Keywords

automatic testing; combinatorial circuits; integrated circuit testing; integrated logic circuits; logic testing; ICAT; ISCAS circuits; circuit modification; combinational circuits; deterministic test generation algorithm; incremental combinational ATPG; modified circuit; Automatic test pattern generation; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Design for testability; Electrical fault detection; Fault detection; Sequential analysis; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1994. Proceedings., 12th IEEE

Conference_Location

Cherry Hill, NJ

Print_ISBN

0-8186-5440-6

Type

conf

DOI

10.1109/VTEST.1994.292326

Filename

292326