DocumentCode
1872061
Title
Discrete test generation by continuous methods
Author
Rivin, Igor ; Chakradhar, Srimat T.
Author_Institution
Sch. of Math., Inst. for Adv. Study, Princeton, NJ, USA
fYear
1994
fDate
25-28 Apr 1994
Firstpage
100
Lastpage
105
Abstract
We describe a continuous optimization approach for the test generation of combinational circuits. We extend the domain of signal values from the traditional Boolean 0 or 1 value to the real unit interval [0, 1]. Responses of Boolean gates comprising the circuit are also extended to deal with real input values. Non-linear smooth functions are constructed for every gate. A non-linear continuous function for the entire circuit is obtained as a summation of the individual gate functions. A similar function is derived for the faulty circuit. We construct an objective function using the good and faulty circuit functions. The objective function is minimized when at least one of the corresponding outputs of the good and faulty circuit differ. The test generation problem is formulated as the minimization of the objective function over a unit hypercube in the Euclidean space. The dimension of the space is equal to the number of primary inputs of the circuit. We optimize the smooth function inside a convex polytope using a variant of gradient descent and line search strategies. We start at the center of the hypercube and follow a trajectory to one of the corners of the hypercube that corresponds to a test vector. Preliminary experimental results on the ISCAS ´85 and ´89 benchmark circuits demonstrate the feasibility of our approach
Keywords
Boolean functions; combinatorial circuits; integrated circuit testing; integrated logic circuits; logic testing; minimisation; Boolean gates; Euclidean space; combinational circuits; continuous methods; continuous optimization; convex polytope; discrete test generation; faulty circuit function; gradient descent; line search; minimization; nonlinear continuous function; nonlinear smooth functions; objective function; unit hypercube; Benchmark testing; Circuit faults; Circuit testing; Combinational circuits; Hypercubes; Mathematics; National electric code; Neural networks; Signal generators; Space exploration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1994. Proceedings., 12th IEEE
Conference_Location
Cherry Hill, NJ
Print_ISBN
0-8186-5440-6
Type
conf
DOI
10.1109/VTEST.1994.292327
Filename
292327
Link To Document